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1 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 typical application features applications description 12-bit, 125msps/105msps/ 80msps low power quad adcs ltc2175-12, 125msps, 2-tone fft, f in = 70mhz and 75mhz the ltc ? 2175-12/2174-12/2173-12 are 4-channel, simul- taneous sampling 12-bit a/d converters designed for digitizing high frequency, wide dynamic range signals. they are perfect for demanding communications applica- tions with ac performance that includes 70.6db snr and 88db spurious free dynamic range (sfdr). ultralow jitter of 0.15ps rms allow s under s ampling of if fr equencies w i th excellent noise performance. dc specs include 0.3lsb inl (typ), 0.1lsb dnl (typ) and no missing codes over temperature. the transition noise is a low 0.3lsb rms . the digital outputs are serial lvds to minimize the num- ber of data lines. each channel outputs two bits at a time (2-lane mode). at lower sampling rates there is a one bit per channel option (1-lane mode). the lvds drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl, or cmos inputs. an internal clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. n 4-channel simultaneous sampling adc n 70.6db snr n 88db sfdr n low power: 545mw/439mw/369mw total, 136mw/110mw/92mw per channel n single 1.8v supply n serial lvds outputs: 1 or 2 bits per channel n selectable input ranges: 1v p-p to 2v p-p n 800mhz full power bandwidth s/h n shutdown and nap modes n serial spi port for con? guration n pin compatible 14-bit and 12-bit versions n 52-pin (7mm 8mm) qfn package n communications n cellular base stations n software de? ned radios n portable medical imaging n multichannel data acquisition n nondestructive testing l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 50 60 217512 ta01b data serializer encode input serialized lvds outputs 1.8v v dd 1.8v ov dd out1a out1b out2a out2b out3a out3b out4a out4b data clock out frame ognd gnd 217512 ta01 s/h channel 1 analog input 12-bit adc core s/h channel 2 analog input 12-bit adc core s/h channel 3 analog input 12-bit adc core s/h channel 4 analog input 12-bit adc core pll
ltc2175-12/ LTC2174-12/ltc2173-12 2 21754312f absolute maximum ratings (notes 1, 2) pin configurations order information lead free finish tape and reel part marking* package description temperature range ltc2175cukg-12#pbf ltc2175cukg-12#trpbf ltc2175ukg-12 52-lead (7mm 8mm) plastic qfn 0c to 70c ltc2175iukg-12#pbf ltc2175iukg-12#trpbf ltc2175ukg-12 52-lead (7mm 8mm) plastic qfn C40c to 85c ltc2174cukg-12#pbf ltc2174cukg-12#trpbf ltc2174ukg-12 52-lead (7mm 8mm) plastic qfn 0c to 70c ltc2174iukg-12#pbf ltc2174iukg-12#trpbf ltc2174ukg-12 52-lead (7mm 8mm) plastic qfn C40c to 85c ltc2173cukg-12#pbf ltc2173cukg-12#trpbf ltc2173ukg-12 52-lead (7mm 8mm) plastic qfn 0c to 70c ltc2173iukg-12#pbf ltc2173iukg-12#trpbf ltc2173ukg-12 52-lead (7mm 8mm) plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *t he temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ supply voltages v dd , ov dd ................................................ C0.3v to 2v analog input voltage (a in + , a in C , par/ ser , sense) (note 3) ...........C0.3v to (v dd + 0.2v) digital input voltage (enc + , enc C , cs , sdi, sck) (note 4) .................................... C0.3v to 3.9v sdo (note 4) ............................................ C0.3v to 3.9v digital output voltage ................ C0.3v to (ov dd + 0.3v) operating temperature range ltc2175c, 2174c, 2173c ........................ 0c to 70c ltc2175i, 2174i, 2173i ....................... C40c to 85c storage temperature range ................... C65c to 150c 16 15 17 18 19 top view 53 gnd ukg package 52-lead (7mm 8mm) plastic qfn 20 21 22 23 24 25 26 51 52 50 49 48 47 46 45 44 43 42 41 33 34 35 36 37 38 39 40 8 7 6 5 4 3 2 1 a in1 + a in1 C v cm12 a in2 + a in2 C refh refh refl refl a in3 + a in3 C v cm34 a in4 + a in4 C out2a + out2a C out2b + out2b C dco + dco C ov dd ognd fr + fr C out3a + out3a C out3b + out3b C v dd v dd sense gnd v ref par/ ser sdo gnd out1a + out1a C out1b + out1b C v dd v dd enc + enc C cs sck sdi gnd out4b C out4b + out4a C out4a + 32 31 30 29 28 27 9 10 11 12 13 14 t jmax = 150c, ja = 28c/w exposed pad (pin 53) is gnd, must be soldered to pcb
3 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 converter characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 5) parameter conditions ltc2175-12 LTC2174-12 ltc2173-12 units min typ max min typ max min typ max resolution (no missing codes) l 12 12 12 bits integral linearity error differential analog input (note 6) l C1 0.3 1 C1 0.3 1 C1 0.3 1 lsb differential linearity error differential analog input l C0.4 0.1 0.4 C0.4 0.1 0.4 C0.4 0.1 0.4 lsb offset error (note 7) l C12 3 12 C12 3 12 C12 3 12 mv gain error internal reference external reference l C2.8 C1.3 C1.3 0.2 C2.8 C1.3 C1.3 0.2 C2.8 C1.3 C1.3 0.2 %fs %fs offset drift 20 20 20 v/c full-scale drift internal reference external reference 35 25 35 25 35 25 ppm/c ppm/c gain matching external reference 0.2 0.2 0.2 %fs offset matching 3 3 3 mv transition noise external reference 0.3 0.3 0.3 lsb rms analog input the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 1.7v < v dd < 1.9v l 1 to 2 v p-p v in(cm) analog input common mode (a in + + a in C )/2 differential analog input (note 8) l v cm C 100mv v cm v cm + 100mv v v sense external voltage reference applied to sense external reference mode l 0.625 1.250 1.300 v i incm analog input common mode current per pin, 125msps per pin, 105msps per pin, 80msps 155 130 100 a a a i in1 analog input leakage current no encode 0 < a in + , a in C < v dd , l C1 1 a i in2 par/ ser input leakage current 0 < par/ ser < v dd l C3 3 a i in3 sense input leakage current 0.625 < sense < 1.3v l C6 6 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay jitter 0.15 ps rms cmrr analog input common mode rejection ratio 80 db bw-3b full-power bandwidth figure 6 test circuit 800 mhz
ltc2175-12/ LTC2174-12/ltc2173-12 4 21754312f dynamic accuracy the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions ltc2175-12 LTC2174-12 ltc2173-12 units min typ max min typ max min typ max snr signal-to-noise ratio 5mhz input 70mhz input 140mhz input l 69.3 70.6 70.6 70.3 69.2 70.6 70.5 70.3 69.3 70.6 70.5 70.3 dbfs dbfs dbfs sfdr spurious free dynamic range 2nd or 3rd harmonic 5mhz input 70mhz input 140mhz input l 74 88 85 82 74 88 85 82 76 88 85 82 dbfs dbfs dbfs spurious free dynamic range 4th harmonic or higher 5mhz input 70mhz input 140mhz input l 84 90 90 90 84 90 90 90 85 90 90 90 dbfs dbfs dbfs s/(n+d) signal-to-noise plus distortion ratio 5mhz input 70mhz input 140mhz input l 68.6 70.6 70.4 70 68.7 70.6 70.4 70 68.9 70.6 70.4 70 dbfs dbfs dbfs crosstalk, near channel 10mhz input (note 12) C90 C90 C90 dbc crosstalk, far channel 10mhz input (note 12) C105 C105 C105 dbc internal reference characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (note 5) parameter conditions min typ max units v cm output voltage i out = 0 0.5 ? v dd C 25mv 0.5 ? v dd 0.5 ? v dd + 25mv v v cm output temperature drift 25 ppm/c v cm output resistance C600a < i out < 1ma 4 v ref output voltage i out = 0 1.225 1.250 1.275 v v ref output temperature drift 25 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v
5 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 digital inputs and outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 5) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) differential encode mode (enc C not tied to gnd) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.6 v v v in input voltage range enc + , enc C to gnd l 0.2 3.6 v r in input resistance (see figure 10) 10 k c in input capacitance 3.5 pf single-ended encode mode (enc C tied to gnd) v ih high level input voltage v dd = 1.8v l 1.2 v v il low level input voltage v dd = 1.8v l 0.6 v v in input voltage range enc + to gnd l 0 3.6 v r in input resistance (see figure 11) 30 k c in input capacitance 3.5 pf digital inputs ( cs , sdi, sck in serial or parallel programming mode. sdo in parallel programming mode) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance 3pf sdo output (serial programming mode. open-drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd = 1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance 3pf digital data outputs v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 247 125 350 175 454 250 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 1.125 1.125 1.250 1.250 1.375 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100
ltc2175-12/ LTC2174-12/ltc2173-12 6 21754312f power requirements the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 9) symbol parameter conditions ltc2175-12 LTC2174-12 ltc2173-12 units min typ max min typ max min typ max v dd analog supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v i vdd analog supply current sine wave input l 276 300 218 240 180 196 ma i ovdd digital supply current 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode l l 27 49 31 54 26 48 31 53 25 47 29 52 ma ma p diss power dissipation 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode l l 545 585 596 637 439 479 488 527 369 409 405 446 mw mw p sleep sleep mode power 1 1 1 mw p nap nap mode power 85 85 85 mw p diffclk power increase with differential encode mode enabled (no increase for sleep mode) 20 20 20 mw timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 5) symbol parameter conditions ltc2175-12 LTC2174-12 ltc2173-12 units min typ max min typ max min typ max f s sampling frequency (notes 10,11) l 5 125 5 105 5 80 mhz t encl enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 3.8 2 4 4 100 100 4.52 2 4.76 4.76 100 100 5.93 2 6.25 6.25 100 100 ns ns t ench enc high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 3.8 2 4 4 100 100 4.52 2 4.76 4.76 100 100 5.93 2 6.25 6.25 100 100 ns ns t ap sample-and-hold acquisition delay time 000ns symbol parameter conditions min typ max units digital data outputs (r term = 100 differential, c l = 2pf to gnd on each output) t ser serial data bit period 2-lanes, 16-bit serialization 2-lanes, 14-bit serialization 2-lanes, 12-bit serialization 1-lane, 16-bit serialization 1-lane, 14-bit serialization 1-lane, 12-bit serialization 1/(8 ? f s ) 1/(7 ? f s ) 1/(6 ? f s ) 1/(16 ? f s ) 1/(14 ? f s ) 1/(12 ? f s ) s s s s s s t frame fr to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser s t data data to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser s t pd propagation delay (note 8) l 0.7n + 2 ? t ser 1.1n + 2 ? t ser 1.5n + 2 ? t ser s t r output rise time data, dco, fr, 20% to 80% 0.17 ns t f output fall time data, dco, fr, 20% to 80% 0.17 ns dco cycle-cycle jitter t ser = 1ns 60 ps p-p pipeline latency 6 cycles
7 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 symbol parameter conditions min typ max units spi port timing (note 8) t sck sck period write mode readback mode, c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs to sck setup time l 5ns t h sck to cs setup time l 5ns t ds sdi setup time l 5ns t dh sdi hold time l 5ns t do sck falling to sdo valid readback mode, c sdo = 20pf, r pullup = 2k l 125 ns timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 5) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v, f sample = 125mhz (ltc2175), 105mhz (ltc2174), or 80mhz (ltc2173), 2-lane output mode, differential enc + / enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is de? ned as the deviation of a code from a best ? t straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5 lsb when the output code ? ickers between 0000 0000 0000 and 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: v dd = ov dd = 1.8v, f sample = 125mhz (ltc2175), 105mhz (ltc2174), or 80mhz (ltc2173), 2-lane output mode, enc + = single- ended 1.8v square wave, enc C = 0v, input range = 2v p-p with differential drive, unless otherwise noted. the supply current and power dissipation speci? cations are totals for the entire chip, not per channel. note 10: recommended operating conditions. note 11: the maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. the maximum serial data rate is 1000mbps so t ser must be greater than or equal to 1ns. note 12: near-channel crosstalk refers to ch. 1 to ch.2, and ch.3 to ch.4. far-channel crosstalk refers to ch.1 to ch.3, ch.1 to ch.4, ch.2 to ch.3, and ch.2 to ch.4.
ltc2175-12/ LTC2174-12/ltc2173-12 8 21754312f 2-lane output mode, 14-bit serialization analog input enc C enc + dco C dco + t ap t ench t encl t ser t ser t ser t pd t data t frame sample n-6 sample n-5 sample n-4 sample n-3 n+1 n+2 n 217512 td02 d5 d3 d1 d x * d11 d9 d7 d5 d3 d1 d x * d11 d9 d7 d5 d3 d1 d11 d9 d7 out#a C out#a + fr C fr + d4 d2 d0 d y * d10 d8 d6 d4 d2 d0 d y * d x * d y * d10 d8 d6 d4 d2 d0 d10 d8 d6 out#b C out#b + note that in this mode fr + /fr C has two times the period of enc + /enc C *d x and d y are extra non-data bits for complete software compatibility with the 14-bit versions of these a/ds. during normal non-overranged operation d x and d y are set to logic 0. see the data format section for more details. timing diagrams 2-lane output mode, 16-bit serialization analog input enc C enc + dco C dco + t ap t ench t encl t ser t ser t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n 217512 td01 d3 d1 d x * 0 d11 d9 d7 d5 d3 d1 d x * 0 d11 d9 d7 out#a C out#a + fr C fr + d2 d0 d y * 0 d10 d8 d6 d4 d2 d0 d y * 0 d10 d8 d6 out#b C out#b + *d x and d y are extra non-data bits for complete software compatibility with the 14-bit versions of these a/ds. during normal non-overranged operation d x and d y are set to logic 0. see the data format section for more details.
9 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 timing diagrams 2-lane output mode, 12-bit serialization 1-lane output mode, 16-bit serialization analog input enc C enc + dco C dco + t ap t ench t encl t ser t ser t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n 217512 td03 d7 d5 d3 d1 d11 d9 d7 d5 d3 d1 d11 d9 d7 out#a C out#a + fr + fr C d6 d4 d2 d0 d10 d8 d6 d4 d2 d0 d10 d8 d6 out#b C out#b + analog input enc C enc + dco C dco + t ap t ench t encl t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n t ser t ser 217512 td05 d x *d y *d x *d y * 0 0 d11 d10 d9 d8 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 d11 out#a C out#a + fr C fr + out#b + , out#b C are disabled *d x and d y are extra non-data bits for complete software compatibility with the 14-bit versions of these a/ds. during normal non-overranged operation d x and d y are set to logic 0. see the data format section for more details.
ltc2175-12/ LTC2174-12/ltc2173-12 10 21754312f timing diagrams one-lane output mode, 14-bit serialization analog input enc C enc + dco C dco + t ap t ench t encl t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n t ser t ser 217512 td06 d1 d0 d x *d x *d y * d y * d11 d10 d9 d8 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d11 out#a C out#a + fr C fr + out#b + , out#b C are disabled *d x and d y are extra non-data bits for complete software compatibility with the 14-bit versions of these a/ds. during normal non-overranged operation d x and d y are set to logic 0. see the data format section for more details. one-lane output mode, 12-bit serialization analog input enc C enc + dco C dco + t ap t ench t encl t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n t ser t ser 217512 td07 d3 d2 d1 d0 d11 d10 d9 d8 d10 d9 d7 d6 d5 d4 d3 d2 d1 d0 d11 out#a C out#a + fr C fr + out#b + , out#b C are disabled a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/ w sdo high impedance t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 217512 td04 cs sck sdi r/ w sdo high impedance spi port timing (readback mode) spi port timing (write mode)
11 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 typical performance characteristics ltc2175-12: integral nonlinearity (inl) ltc2175-12: differential nonlinearity (dnl) ltc2175-12: 8k point fft, f in = 5mhz C1dbfs, 125msps output code 0 C1.0 C0.4 C0.6 C0.8 inl error (lsb) C0.2 0 0.2 0.8 0.4 0.6 1.0 1024 2048 3072 4096 217512 g01 output code 0 C1.0 C0.4 C0.2 C0.6 C0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 1024 2048 3072 4096 217512 g02 frequency (mhz) C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 217512 g03 0 10 20 30 40 50 60 ltc2175-12: 8k point fft, f in = 30mhz C1dbfs, 125msps ltc2175-12: 8k point fft, f in = 70mhz C1dbfs, 125msps ltc2175-12: 8k point fft, f in = 140mhz C1dbfs, 125msps ltc2175-12: 8k point 2-tone fft, f in = 70mhz, 75mhz, C1 dbfs, 125msps ltc2175-12: shorted input histogram frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 217512 g04 10 20 30 40 50 60 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 50 60 217512 g05 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 50 60 217512 g06 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 50 60 217512 g07 output code 2041 2042 2044 2000 0 10000 8000 6000 4000 count 12000 16000 14000 18000 2043 2045 217512 g08 input frequency (mhz) 0 72 71 70 69 68 67 66 snr (dbfs) 50 100 150 200 250 300 350 217512 g09 ltc2175-12: snr vs input frequency, C1db, 2v range, 125msps
ltc2175-12/ LTC2174-12/ltc2173-12 12 21754312f typical performance characteristics ltc2175-12: sfdr vs input level, f in = 70mhz, 2v range, 125msps ltc2175-12: i vdd vs sample rate, 5mhz sine wave input, C1db input level (dbfs) C80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 C70 C60 C50 C40 C30 C20 C10 0 217512 g12 dbfs dbc input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 217512 g10 ltc2175-12: sfdr vs input frequency, C1db, 2v range, 125msps io vdd vs sample ra te, 5mhz sine wave input, C1db ltc2175-12: snr vs sense, f in = 5mhz, C1db LTC2174-12: integral nonlinearity (inl) LTC2174-12: differential nonlinearity (dnl) LTC2174-12: 8k point fft, f in = 5mhz C1dbfs, 105msps sense pin (v) 0.6 71 68 69 70 67 66 72 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 217512 g15 output code 0 C1.0 C0.4 C0.6 C0.8 inl error (lsb) C0.2 0 0.2 0.4 0.6 0.8 1.0 1024 2048 3072 4096 217512 g21 output code 0 C1.0 C0.4 C0.2 C0.6 C0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 1024 2048 3072 4096 217512 g22 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 50 217512 g23 sample rate (msps) 290 280 270 260 250 240 230 220 210 i vdd (ma) 0 25 50 75 100 125 217512 g53 sample rate (msps) 50 40 30 20 10 0 io vdd (ma) 0 25 50 75 100 125 217512 g51 1-lane, 1.75ma 2-lane, 3.5ma 2-lane, 1.75ma 1-lane, 3.5ma input level (dbfs) 60 50 40 30 20 10 0 80 70 snr (dbc and dbfs) C60 C50 C40 C30 C20 C10 0 217512 g50 dbfs dbc ltc2175-12: snr vs input level, f in = 70mhz, 2v range, 125msps
13 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 LTC2174-12: i vdd vs sample rate, 5mhz sine wave input, C1db LTC2174-12: shorted input histogram LTC2174-12: sfdr vs input level, f in = 70mhz, 2v range, 105msps typical performance characteristics output code 2044 2000 0 6000 4000 count 8000 16000 14000 12000 10000 18000 2046 2047 2045 2048 217512 g28 input level (dbfs) C80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 C70 C60 C50 C40 C30 C20 C10 0 217512 g32 dbfs dbc input frequency (mhz) 0 72 71 70 69 68 67 66 snr (dbfs) 50 100 150 200 250 300 350 217512 g29 input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 217512 g23a LTC2174-12: snr vs input frequency, C1db, 2v range, 105msps LTC2174-12: sfdr vs input frequency, C1db, 2v range, 105msps LTC2174-12: 8k point fft, f in = 70mhz C1dbfs, 105msps LTC2174-12: 8k point fft, f in = 140mhz C1dbfs, 105msps frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 50 217512 g25 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 50 217512 g26 LTC2174-12: 8k point 2-tone fft, f in = 70mhz, 75mhz, C1 dbfs, 105msps frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 50 217512 g27 sample rate (msps) 230 220 210 200 190 180 170 160 i vdd (ma) 0 25 50 75 100 217512 g54 LTC2174-12: 8k point fft, f in = 30mhz C1dbfs, 105msps frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 50 217512 g24
ltc2175-12/ LTC2174-12/ltc2173-12 14 21754312f LTC2174-12: snr vs sense, f in = 5mhz, C1db sense pin (v) 0.6 71 68 69 70 67 66 72 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 217512 g35 typical performance characteristics ltc2173-12: 8k point 2-tone fft, f in = 70mhz, 75mhz, C1 dbfs, 80msps ltc2173-12: shorted input histogram ltc2173-12: 8k point fft, f in = 30mhz C1dbfs, 80msps ltc2173-12: 8k point fft, f in = 70mhz C1dbfs, 80msps ltc2173-12: 8k point fft, f in = 140mhz C1dbfs, 80msps ltc2173-12: integral nonlinearity (inl) ltc2173-12: differential nonlinearity (dnl) ltc2173-12: 8k point fft, f in = 5mhz C1dbfs, 80msps output code 0 C1.0 C0.4 C0.2 C0.6 C0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 1024 2048 3072 4096 217512 g42 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 217512 g43 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 217512 g44 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 217512 g45 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 217512 g46 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 217512 g47 output code 2052 2000 4000 6000 8000 0 12000 10000 count 14000 16000 18000 2054 2053 2056 2055 217512 g48 output code 0 C1.0 C0.4 C0.6 C0.8 inl error (lsb) C0.2 0 0.4 0.6 0.2 0.8 1.0 1024 2048 3072 4096 217512 g41
15 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 typical performance characteristics ltc2173-12: i vdd vs sample rate, 5mhz sine wave input, C1db dco cycle-cycle jitter vs serial data rate ltc2173-12: snr vs sense, f in = 5mhz, C1db sense pin (v) 0.6 71 68 69 70 67 66 72 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1.0 217512 g55a ltc2173-12: sfdr vs input level, f in = 70mhz, 2v range, 80msps input level (dbfs) C80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 C70 C60 C50 C40 C30 C20 C10 0 217512 g52 dbfs dbc input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 217512 g35a ltc2173-12: sfdr vs input frequency, C1db, 2v range, 80msps input frequency (mhz) 0 72 71 70 69 68 67 66 snr (dbfs) 50 100 150 200 250 300 350 217512 g49 ltc2173-12: snr vs input frequency, C1db, 2v range, 80msps serial data rate (mbps) 350 300 250 200 150 100 50 0 peak-to-peak jitter (ps) 0 200 400 600 800 1000 217512 g52a sample rate (msps) 190 170 180 160 150 140 i vdd (ma) 02040 80 60 217512 g55
ltc2175-12/ LTC2174-12/ltc2173-12 16 21754312f pin functions a in1 + (pin 1): channel 1 positive differential analog input. a in1 C (pin 2): channel 1 negative differential analog input. v cm12 (pin 3): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channels 1 and 2. bypass to ground with a 0.1f ceramic capacitor. a in2 + (pin 4): channel 2 positive differential analog input. a in2 C (pin 5): channel 2 negative differential analog input. refh (pins 6,7): a dc high re fer enc e. b ypa s s to pins 8, 9 with a 2.2f ceramic capacitor and to ground with a 0.1f ceramic capacitor. refl (pins 8,9): adc low reference. bypass to pins 6, 7 with a 2.2f ceramic capacitor and to ground with a 0.1f ceramic capacitor. a in3 + (pin 10): channel 3 positive differential analog input. a in3 C (pin 11): channel 3 negative differential analog input. v cm34 (pin 12): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channels 3 and 4. bypass to ground with a 0.1f ceramic capacitor. a in4 + (pin 13): channel 4 positive differential analog input. a in4 C (pin 14): channel 4 negative differential analog input. v dd (pins 15, 16, 51, 52): analog power supply, 1.7v to 1.9v. bypass to ground with 0.1f ceramic capacitors. adjacent pins can share a bypass capacitor. enc + (pin 17): encode input. conversion starts on the rising edge. enc C (pin 18): encode complement input. conversion starts on the falling edge. cs (pin 19): in serial programming mode, (par/ ser = 0v), cs is the serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in the parallel programming mode (par/ ser = v dd ), cs selects 2-lane or 1-lane output mode. cs can be driven with 1.8v to 3.3v logic. sck (pin 20): in serial programming mode, (par/ ser = 0v), sck is the serial interface clock input. in the parallel programming mode (par/ ser = v dd ), sck selects 3.5ma or 1.75ma lvds output currents. sck can be driven with 1.8v to 3.3v logic. sdi (pin 21): in serial programming mode, (par/ ser = 0v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in the parallel programming mode (par/ ser = v dd ), sdi can be used to power down the part. sdi can be driven with 1.8v to 3.3v logic. gnd (pins 22, 45, 49, exposed pad pin 53): adc power ground. the exposed pad must be soldered to the pcb ground. ognd (pin 33): output driver ground. must be shorted to the ground plane by a very low inductance path. use multiple vias close to the pin. ov dd (pin 34): output driver suppl y, 1.7 v to 1.9v. b ypass to ground with a 0.1f ceramic capacitor. sdo (pin 46): in serial programming mode, (par/ ser = 0v), sdo is the optional serial interface data output. data on sdo is read back from the mode control registers and can be latched on the falling edge of sck. sdo is an open-drain nmos output that requires an external 2k pull-up resistor to 1.8v C 3.3v. if read back from the mode control registers is not needed, the pull-up resistor is not necessary and sdo can be left unconnected. in the parallel programming mode (par/ ser = v dd ), s d o i s a n i n p u t t h a t enables internal 100 termination resistors on the digital outputs. when used as an input, sdo can be driven with 1.8v to 3.3v logic through a 1k series resistor. par/ ser (pin 47): programming mode selection pin. connect to ground to enable the serial programming mode. cs , sck, sdi, sdo become a serial interface that control the a/d operating modes. connect to v dd to enable the parallel programming mode where cs , sck, sdi, sdo become parallel logic inputs that control a reduced set of the a/d operating modes. par/ ser should be connected
17 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 pin functions directly to ground or the v dd of the part and not be driven by a logic signal. v ref (pin 48): reference voltage output. bypass to ground with a 1f ceramic capacitor, nominally 1.25v. sense (pin 50): reference programming pin. connecting sense to v dd selects the internal reference and a 1v input range. connecting sense to ground selects the internal reference and a 0.5v input range. an external reference between 0.625v and 1.3v applied to sense selects an input range of 0.8 ? v sense . lvds outputs all pins in this section are differential lvds outputs. the output current level is programmable. there is an optional internal 100 termination resistor between the pins of each lvds output pair. out4b C /out4b + , out4a C /out4a + (pins 23/24, pins 25/26): serial data outputs for channel 4. in 1-lane output mode only out4a C /out4a + are used. out3b C /out3b + , out3a C /out3a + (pins 27/28, pins 29/30): serial data outputs for channel 3. in 1-lane output mode only out3a C /out3a + are used. fr C /fr + (pins 31/32): frame start outputs. dco C /dco + (pins 35/36): data clock outputs. out2b C /out2b + , out2a C /out2a + (pins 37/38, pins 39/40): serial data outputs for channel 2. in 1-lane output mode only out2a C /out2a + are used. out1b C /out1b + , out1a C /out1a + (pins 41/42, pins 43/44): serial data outputs for channel 1. in 1-lane output mode only out1a C /out1a + are used.
ltc2175-12/ LTC2174-12/ltc2173-12 18 21754312f functional block diagram figure 1. functional block diagram diff ref amp ref buf 2.2f 0.1f 0.1f 0.1f 0.1f refh refl range select 1.25v reference v dd /2 v dd 1.8v refh gnd refl vcm12 vcm34 data serializer ognd 217512 f01 s/h s/h s/h s/h sense v ref 1f 0.1f 12-bit adc core 12-bit adc core 12-bit adc core 12-bit adc core ov dd 1.8v enc + enc C pll out1a C out1a + out1b C out1b + out2a C out2a + out2b C out2b + data clock out + data clock out C out3a C out3a + out3b C out3b + out4a C out4a + out4b C out4b + frame + frame C sdo cs mode control registers sck par/ ser sdi channel 1 analog input + channel 1 analog input C channel 2 analog input + channel 2 analog input C channel 3 analog input + channel 3 analog input C channel 4 analog input + channel 4 analog input C
19 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 applications information converter operation the ltc2175-12/LTC2174-12/ltc2173-12 are low power, 4-channel, 12-bit, 125msps/105msps/80msps a /d con- verters that are powered by a single 1.8v supply. the analog inputs should be driven differentially. the encode input can be driven differentially for optimal jitter perfor- mance, or single-ended for lower power consumption. the digital outputs are serial lvds to minimize the number of data lines. each channel outputs two bits at a time (2-lane mode). at lower sampling rates there is a one bit per channel option (1-lane mode). many additional features can be chosen by programming the mode control registers through a serial spi port. analog input the analog inputs are differential cmos sample-and-hold circuits (figure 2). the inputs should be driven differen- tially around a common mode voltage set by the v cm12 or v cm34 output pins, which are nominally v dd /2. for the 2v input range, the inputs should swing from v cm C 0.5v to v cm + 0.5v. there should be 180 phase difference between the inputs. the four channels are simultaneously sampled by a shared encode circuit (figure 2). input drive circuits input filtering if possible, there should be an rc low pass ? lter right at the analog inputs. this lowpass ? lter isolates the drive circuitry from the a/d sample-and-hold switching, and also limits wideband noise from the drive circuitry. figure 3 shows an example of an input rc ? lter. the rc component values should be chosen base d on the applications input frequency. transformer coupled circuits figure 3 shows the analog input being driven by an rf transformer with a center-tapped secondary. the center figure 2. equivalent input circuit. only one of the four analog channels is shown. c sample 3.5pf r on 25 r on 25 v dd v dd ltc2175-12 a in + 217512 f02 c sample 3.5pf v dd a in C enc C enc + 1.2v 10k 1.2v 10k c parasitic 1.8pf c parasitic 1.8pf 10 10 figure 3. analog input circuit using a transformer. recommended for input frequencies from 5mhz to 70mhz. 25 25 25 25 50 0.1f a in + a in C 12pf 0.1f v cm ltc2175-12 analog input 0.1f t1 1:1 t1: ma/com mabaes0060 resistors, capacitors are 0402 package size 217512 f03
ltc2175-12/ LTC2174-12/ltc2173-12 20 21754312f applications information tap is biased with v cm , setting the a/d input at its opti- mal dc level. at higher input frequencies a transmission line balun transformer (figures 4 to 6) has better balance, resulting in lower a/d distortion. ampli? er circuits figure 7 shows the analog input being driven by a high speed differential ampli? er. the output of the ampli? er is ac-coupled to the a/d so the ampli? ers output common mode voltage can be optimally set to minimize distor- tion. figure 4. recommended front end circuit for input frequencies from 70mhz to 170mhz 25 25 50 0.1f a in + a in C 4.7pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: ma/com mabaes0060 resistors, capacitors are 0402 package size 217512 f04 ltc2175-12 25 25 50 0.1f a in + a in C 1.8pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1lb resistors, capacitors are 0402 package size 217512 f05 ltc2175-12 25 25 50 0.1f 2.7nh 2.7nh a in + a in C 0.1f v cm analog input 0.1f 0.1f t1 t1: ma/com etc1-1-13 resistors, capacitors are 0402 package size 217512 f06 ltc2175-12 25 25 200 200 0.1f a in + a in C 12pf 0.1f v cm ltc2175-12 217512 f07 C C + + analog input high speed differential amplifier 0.1f at very high frequencies an rf gain block will often have lower distortion than a differential ampli? er. if the gain block is single-ended, then a transformer circuit (figures 4 to 6) should convert the signal to differential before driving the a/d. reference the ltc2175-12/LTC2174-12/ltc2173-12 has an internal 1.25v voltage reference. for a 2v input range using the internal reference, connect sense to v dd . for a 1v input range using the internal reference, connect sense to figure 5. recommended front end circuit for input frequencies from 170mhz to 300mhz figure 6. recommended front end circuit for input frequencies above 300mhz figure 7. front end circuit using a high speed differential ampli? er
21 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 applications information figure 8. reference circuit figure 9. using an external 1.25v reference ground. for a 2v input range with an external reference, apply a 1.25v reference voltage to sense (figure 9). the input range can be adjusted by applying a voltage to sense that is between 0.625v and 1.30v. the input range will then be 1.6 ? v sense . the reference is shared by all four adc channels, so it is not possible to independently adjust the input range of individual channels. the v ref , refh and refl pins should be bypassed as shown in figure 8. the 0.1f capacitor between refh figure 10. equivalent encode input circuit for differential encode mode and refl should be as close to the pins as possible (not on the backside of the circuit board). encode input the signal quality of the encode inputs strongly affects the a/d noise performance. the encode inputs should be treated as analog signalsdo not route them next to digital traces on the circuit board. there are two modes of operation for the encode inputs: the differential encode mode (figure 10), and the single-ended encode mode (figure 11). v ref refh sense tie to v dd for 2v range; tie to gnd for 1v range; range = 1.6 ? v sense for 0.65v < v sense < 1.300v 1.25v refl 0.1f 2.2f internal adc high reference buffer 5 0.8x diff amp internal adc low reference 1.25v bandgap reference 0.625v range detect and control 1f 0.1f 0.1f 217512 f08 ltc2175-12 sense 1.25v external reference 1f 1f v ref 217512 f09 ltc2175-12 v dd ltc2175-12 217512 f10 enc C enc + 15k v dd differential comparator 30k 30k enc + enc C 217512 f11 0v 1.8v to 3.3v ltc2175-12 cmos logic buffer figure 11. equivalent encode input circuit for single-ended encode mode
ltc2175-12/ LTC2174-12/ltc2173-12 22 21754312f applications information the differential encode mode is recommended for sinu- soidal, pecl, or lvds encode inputs (figures 12 and 13). the encode inputs are internally biased to 1.2v through 10k equivalent resistance. the encode inputs can be taken above v dd (up to 3.6v), and the common mode range is from 1.1v to 1.6v. in the differential encode mode, enc C should stay at least 200mv above ground to avoid falsely triggering the single-ended encode mode. for good jitter performance enc + should have fast rise and fall times. t h e s i n g l e - e n d e d e n c o d e m o d e s h o u l d b e u s e d w i t h c m o s encode inputs. to select this mode, enc C is connected to ground and enc + is driven with a square wave encode input. enc + can be taken above v dd (up to 3.6v) so 1.8v t o 3 . 3 v c m o s l o g i c l e v e l s c a n b e u s e d . t h e e n c + threshold is 0.9v. for good jitter performance enc + s h o ul d h a v e f a s t rise and fall times. clock pll and duty cycle stabilizer the encode clock is multiplied by an internal phase-locked loop (pll) to generate the serial digital output data. if the encode signal changes frequency or is turned off, the pll requires 25s to lock onto the input clock. a clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. in the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. in the parallel programming mode the duty cycle stabilizer is always enabled. figure 13. pecl or lvds encode drive figure 12. sinusoidal encode drive 50 100 0.1f 0.1f 0.1f t1 t1 = ma/com etc1-1-13 resistors and capacitors are 0402 package size 50 ltc2175-12 217512 f12 enc C enc + enc + enc C pecl or lv d s clock 0.1f 0.1f 217512 f13 ltc2175-12
23 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 applications information digital outputs the digital outputs of the ltc2175-12/LTC2174-12/ ltc2173-12 are serialized lvds signals. each channel outputs two bits at a time (2-lane mode). at lower sam- pling rates there is a one bit per channel option (1-lane mode). the data can be serialized with 16, 14, or 12-bit serialization (see timing diagrams for details). the output data should be latched on the rising and falling edges of the data clock out (dco). a data frame output (fr) can be used to determine when the data from a new conversion result begins. in the 2-lane, 14-bit serialization mode, the frequency of the fr output is halved. the maximum serial data rate for the data outputs is 1gbps, so the maximum sample rate of the adc will de- pend on the serialization mode as well as the speed grade of the adc (see table 1). the minimum sample rate for all serialization modes is 5msps. by default the outputs are standard lvds levels: 3.5ma output current and a 1.25v output common mode volt- age. an external 100 differential termination resistor is required for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. programmable lvds output current the default output driver current is 3.5ma. this current can be adjusted by control register a2 in the serial pro- gramming mode. available current levels are 1.75ma, 2.1ma, 2.5ma, 3ma, 3.5ma, 4ma and 4.5ma. in the parallel programming mode the sck pin can select either 3.5ma or 1.75ma. optional lvds driver internal termination in most cases using just an external 100 termination resistor will give excellent lv ds signal integrity. in addi- tion, an optional internal 100 termination resistor can be enabled by serially programming mode control register a2. the internal termination helps absorb any re? ections caused by imperfect termination at the receiver. when the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. in the parallel programming mode the sdo pin enables internal termination. internal termination should only be used with 1.75ma, 2.1ma or 2.5ma lvds output current modes. table 1. maximum sampling frequency for all serialization modes. note that these limits are for the ltc2175-12. the sampling frequency for the slower speed grades cannot exceed 105mhz (LTC2174-12) or 80mhz (ltc2173-12). serialization mode maximum sampling frequency, f s (mhz) dco frequency fr frequency serial data rate 2-lane 16-bit serialization 125 4 ? f s f s 8 ? f s 2-lane 14-bit serialization 125 3.5 ? f s 0.5 ? f s 7 ? f s 2-lane 12-bit serialization 125 3 ? f s f s 6 ? f s 1-lane 16-bit serialization 62.5 8 ? f s f s 16 ? f s 1-lane 14-bit serialization 71.4 7 ? f s f s 14 ? f s 1-lane 12-bit serialization 83.3 6 ? f s f s 12 ? f s
ltc2175-12/ LTC2174-12/ltc2173-12 24 21754312f table 2. output codes vs input voltage a in + C a in C (2v range) d11-d0 (offset binary) d11-d0 (2s complement) d x , d y >+1.000000v +0.999512v +0.999024v 1111 1111 1111 1111 1111 1111 1111 1111 1110 0111 1111 1111 0111 1111 1111 0111 1111 1110 11 00 00 +0.000488v 0.000000v C0.000488v C0.000976v 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 00 00 00 00 C0.999512v C1.000000v ?C1.000000v 0000 0000 0001 0000 0000 0000 0000 0000 0000 1000 0000 0001 1000 0000 0000 1000 0000 0000 00 00 00 applications information data format table 2 shows the relationship between the analog input voltage and the digital data output bits. by default the output data format is offset binary. the 2s complement format can be selected by serially programming mode control register a1. in addition to the 12 data bits (d11 - d0), two additional bits (d x and d y ) are sent out in the 14-bit and 16-bit serialization modes. these extra bits are to ensure com- plete software compatibility with the 14-bit versions of these a/ds. during normal operation when the analog inputs are not overranged, d x and d y are always logic 0. when the analog inputs are overranged positive, d x and d y become logic 1. when the analog inputs are overranged negative, d x and d y become logic 0. d x and d y can also be controlled by the digital output test pattern. see the timing diagrams section for more information. output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. the digital output is randomized by applying an exclusive - or logic operation between the lsb and all other data output bits. to decode, the reverse operation is applied an exclusive-or operation is applied between the lsb and all other bits. the fr and dco outputs are not affected. t h e o u t p u t r a n d o m i z e r i s e n a b l e d b y s e r i a l l y p r o g r a m m i n g mode control register a1. digital output test pattern to allow in-circuit testing of the digital interface to the a/d, there is a test mode that forces the a/d data outputs (d11-d0, d x , d y ) of all channels to known values. the digital output test patterns are enabled by serially program- ming mode control registers a3 and a4. when enabled, the test patterns override all other formatting modes: 2s complement and randomizer. output disable the digital outputs may be disabled by serially program- ming mode control register a2. the current drive for all digital outputs including dco and fr are disabled to save power or enable in-circuit testing. when disabled the com- mon mode of each output pair becomes high impedance, but the differential impedance may remain low. sleep and nap modes the a/d may be placed in sleep or nap modes to conserve power. in sleep mode the entire chip is powered down, resulting in 1mw power consumption. sleep mode is enabled by mode control register a1 (serial programming mode), or by sdi (parallel programming mode). the amount of time required to recover from sleep mode depends on the size of the bypass capacitors on v ref , refh, and refl. for the suggested values in figure 8, the a/d will stabilize after 2ms. digital output randomizer interference from the a/d digital outputs is sometimes u n a v o i d a b l e . d i g i t a l i n t e r f e r e n c e m a y b e f r o m c a p a c i t i v e o r inductive coupling or coupling through the ground plane. even a tiny coupling factor can cause unwanted tones in the adc output spectrum. by randomizing the digital
25 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 applications information in nap mode any combination of a/d channels can be powered down while the internal reference circuits and the pll stay active, allowing faster wakeup than from sleep mode. recovering from nap mode requires at least 100 clock cycles. if the application demands very accurate dc settling then an additional 50s should be allowed so the on-chip references can settle from the slight temperature shift caused by the change in supply current as the a/d leaves nap mode. nap mode is enabled by mode control register a1 in the serial programming mode. device programming modes the operating modes of the ltc2175-12/LTC2174-12/ ltc2173-12 can be programmed by either a parallel inter- face or a simple serial interface. the serial interface has more ? exibility and can program all available modes. the parallel interface is more limited and can only program some of the more commonly used modes. parallel programming mode to use the parallel programming mode, par/ ser should be tied to v dd . the cs , sck, sdi and sdo pins are binary logic inputs that set certain operating modes. these pins can be tied to v dd or ground, or driven by 1.8v, 2.5v, or 3.3v cmos logic. when used as an input, sdo should be driven through a 1k series resistor. table 3 shows the modes set by cs , sck, sdi and sdo. serial programming mode to use the serial programming mode, par/ ser should be tied to ground. the cs , sck, sdi and sdo pins become a serial interface that program the a/d mode control registers. data is written to a register with a 16-bit serial word. data can also be read back from a register to verify its contents. serial data transfer starts when cs is taken low. the data on the sdi pin is latched at the ? rst 16 rising edges of sck. any sck rising edges after the ? rst 16 are ignored. the data transfer ends when cs is taken high again. the ? rst bit of the 16-bit input word is the r/ w bit. the next seven bits are the address of the register (a6:a0). the ? nal eight bits are the register data (d7:d0). if the r/ w bit is low, the serial data (d7:d0) will be writ- ten to the register set by the address bits (a6:a0). if the r/ w bit is high, data in the register set by the address bits (a6:a0) will be read back on the sdo pin (see the timing diagrams sections). during a read back command the register is not updated and data on sdi is ignored. the sdo pin is an open-drain output that pulls to ground w i t h a 2 0 0 i m p e d a n c e . i f r e g i s t e r d a t a i s r e a d b a c k t h r o u g h sdo, an external 2k pull-up resistor is required. if serial data is only written and read back is not needed, then sdo table 3. parallel programming mode control bits (par/ ser = v dd ) pin description cs 2-lane / 1-lane selection bit 0 = 2-lane, 16-bit serialization output mode 1 = 1-lane, 14-bit serialization output mode sck lvds current selection bit 0 = 3.5ma lvds current mode 1 = 1.75ma lvds current mode sdi power down control bit 0 = normal operation 1 = sleep mode sdo internal termination selection bit 0 = internal termination disabled 1 = internal termination enabled
ltc2175-12/ LTC2174-12/ltc2173-12 26 21754312f applications information table 4. serial programming mode register map (par/ ser = gnd) register a0: reset register (address 00h) d7 d6 d5 d4 d3 d2 d1 d0 reset xxxxxxx bit 7 reset software reset bit 0 = not used 1 = software reset. all mode control registers are reset to 00h. the adc is momentarily placed in sleep mode. this bit is automatically set back to zero after the reset is complete bits 6-0 unused, dont care bits. register a1: format and power-down register (address 01h) d7 d6 d5 d4 d3 d2 d1 d0 dcsoff rand twoscomp sleep nap_4 nap_3 nap_2 nap_1 bit 7 dcsoff clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer on 1 = clock duty cycle stabilizer off. this is not recommended. bit 6 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on bit 5 twoscomp twos complement mode control bit 0 = offset binary data format 1 = twos complement data format can be left ? oating and no pull-up resistor is needed. table 4 shows a map of the mode control registers. software reset if serial programming is used, the mode control registers s h o u l d b e p r o g r a m m e d a s s o o n a s p o s s i b l e a f t e r t h e p o w e r supplies turn on and are stable. the ? rst serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset, bit d7 in the reset register is written with a logic 1. after the reset is complete, bit d7 is automatically set back to zero. grounding and bypassing the ltc2175-12/LTC2174-12/ltc2173-12 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an internal ground plane in the ? rst layer beneath the adc is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , v ref , refh and refl pins. bypass capacitors must be located as close to the pins as possible. of particular importance is the 0.1f capacitor between refh and refl. this capacitor should be on the same side of the circuit board as the a/d, and as close to the device as possible (1.5mm or less). size 0402 ceramic capacitors are recommended. the larger 2.2f capacitor between refh and refl can be somewhat further away. t h e t r a c e s c o n n e c t i n g t h e p i n s a n d b y p a s s c a p a c i t o r s m u s t be kept short and should be made as wide as possible. the analog inputs, encode signals, and digital outputs should not be routed next to each other. ground ? ll and grounded vias should be used as barriers to isolate these signals from each other. heat transfer most of the heat generated by the ltc2175-12/LTC2174-12/ ltc2173-12 is transferred from the die through the bot- tom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. this pad should be connected to the internal ground planes by an array of vias.
27 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 applications information bits 4-0 sleep: nap_4:nap_1 sleep/nap mode control bits 00000 = normal operation 0xxx1 = channel 1 in nap mode 0xx1x = channel 2 in nap mode 0x1xx = channel 3 in nap mode 01xxx = channel 4 in nap mode 1xxxx = sleep mode. all channels are disabled note: any combination of channels can be placed in nap mode. register a2: output mode register (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 ilvds2 ilvds1 ilvds0 termon outoff outmode2 outmode1 outmode0 bits 7-5 ilvds2:ilvds0 lvds output current bits 000 = 3.5ma lvds output driver current 001 = 4.0ma lvds output driver current 010 = 4.5ma lvds output driver current 011 = not used 100 = 3.0ma lvds output driver current 101 = 2.5ma lvds output driver current 110 = 2.1ma lvds output driver current 111 = 1.75ma lvds output driver current bit 4 termon lvds internal termination bit 0 = internal termination off 1 = internal termination on. lvds output driver current is 2x the current set by ilvds2:ilvds0. internal termination should on ly be used with 1.75ma, 2.1ma or 2.5ma lvds output current modes. bit 3 outoff output disable bit 0 = digital outputs are enabled. 1 = digital outputs are disabled. bits 2-0 outmode2:outmode0 digital output mode control bits 000 = 2-lanes, 16-bit serialization 001 = 2-lanes, 14-bit serialization 010 = 2-lanes, 12-bit serialization 011 = not used 100 = not used 101 = 1-lane, 14-bit serialization 110 = 1-lane, 12-bit serialization 111 = 1-lane, 16-bit serialization register a3: test pattern msb register (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 outtest x tp11 tp10 tp9 tp8 tp7 tp6 bit 7 outtest digital output test pattern control bit 0 = digital output test pattern off 1 = digital output test pattern on bit 6 unused, dont care bit. bits 5-0 tp11:tp6 test pattern data bits (msb) tp11:tp6 set the test pattern for data bit 11(msb) through data bit 6. register a4: test pattern lsb register (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 tp5 tp4 tp3 tp2 tp1 tp0 tpx tpy bits 7-2 tp5:tp0 test pattern data bits (lsb) tp5:tp0 set the test pattern for data bit 5 through data bit 0(lsb). bit 1-0 tpx:tpy set the test pattern for extra bits d x and d y . these bits are for compatibility with the 14-bit version of the a/d.
ltc2175-12/ LTC2174-12/ltc2173-12 28 21754312f typical applications silkscreen top top side inner layer 2 gnd inner layer 3
29 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 typical applications inner layer 4 inner layer 5 power bottom side silkscreen bottom
ltc2175-12/ LTC2174-12/ltc2173-12 30 21754312f typical applications ltc2175 8 7 6 5 4 3 2 1 a in1 + a in1 C v cm12 a in2 + a in2 C refh refh refl refl a in3 + a in3 C v cm34 a in4 + a in4 C out2a + out2a C out2b + out2b C dco + dco C ov dd ognd fr + fr C out3a + out3a C out3b + out3b C 9 10 11 12 13 14 33 34 35 36 37 38 39 40 32 31 30 29 28 27 v dd v dd enc + enc C cs sck sdi gnd out4b C out4b + out4a C out4a + 16 15 v dd 17 18 19 20 21 22 23 24 25 26 v dd v dd sense gnd v ref par/ ser sdo gnd out1a + out1a C out1b + out1b C 51 52 50 49 48 sdo par/ ser sense 47 46 45 44 43 42 41 c30 0.1f c1 2.2f c59 0.1f r93 100 r94 100 c3 0.1f c2 0.1f c29 0.1f c7 0.1f spi bus digital outputs ov dd c46 0.1f c47 0.1f r92 100 r8 100 a in1 a in1 a in2 a in2 a in3 a in3 a in4 a in4 encode clock encode clock 217512 ta02 r14 1k digital outputs c16 0.1f c4 1f c5 1f c17 1f ltc2175 schematic
31 21754312f ltc2175-12/ LTC2174-12/ltc2173-12 package description information furnished by linear technology corpor ation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- t i o n t h a t t h e i n t e r c o n n e c t i o n o f i t s c i r c u i t s a s d e s c r i b e d h e r e i n w i l l n o t i n f r i n g e o n e x i s t i n g p a t e n t r i g h t s . ukg package 52-lead plastic qfn (7mm 8mm) (reference ltc dwg # 05-08-1729 rev ?) 7.00 0.10 (2 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.30 typ or 0.35 45 c chamfer 0.40 0.10 52 51 1 2 bottom view?xposed pad top view side view 6.50 ref (2 sides) 8.00 0.10 (2 sides) 5.50 ref (2 sides) 0.75 0.05 0.75 0.05 r = 0.115 typ r = 0.10 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ?0.05 6.45 0.10 5.41 0.10 0.00 ?0.05 (ukg52) qfn rev 0306 5.50 ref (2 sides) 5.41 0.05 6.45 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 6.10 0.05 7.50 0.05 6.50 ref (2 sides) 7.10 0.05 8.50 0.05 0.25 0.05 0.50 bsc package outline
ltc2175-12/ LTC2174-12/ltc2173-12 32 21754312f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 1009 ? printed in usa related parts part number description comments adcs ltc2170-14/ltc2171-14/ ltc2172-14 14-bit, 25msps/40msps/65msps 1.8v quad adcs, ultralow power 178mw/234mw/360mw, 73.4db snr, 85db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2170-12/ltc2171-12/ ltc2172-12 12-bit, 25msps/40msps/65msps 1.8v quad adcs, ultralow power 178mw/234mw/360mw, 70.5db snr, 85db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2173-14/ltc2174-14/ ltc2175-14 14-bit, 80 msps /105 msps /125msps 1.8v quad adcs, ultralow power 373mw/445mw/551mw, 73.2 db snr, 88db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2256-14/ltc2257-14/ ltc2258-14 14-bit, 25msps/40msps/65msps msps1.8v adcs, ultralow power 35mw/49mw/81mw, 74db snr, 88db sfdr, ddr lvds/ddr cmos/cmos outputs, 6mm 6mm qfn-36 ltc2259-14/ltc2260-14/ ltc2261-14 14-bit, 80msps/105msps/125msps 1.8v adcs, ultralow power 89mw/106mw/127mw, 73.4db snr, 85db sfdr, ddr lvds/ddr cmos/cmos outputs, 6mm 6mm qfn-36 ltc2262-14 14-bit, 150msps 1.8v adc, ultralow power 149mw, 72.8db snr, 88db sfdr, ddr lvds/ddr cmos/cmos outputs, 6mm 6mm qfn-36 ltc2263-14/ltc2264-14/ ltc2265-14 14-bit, 25msps/40msps/65msps 1.8v dual adcs, ultralow power 99mw/126mw/191mw, 73.4db snr, 85db sfdr, serial lvds outputs, 6mm 6mm qfn-36 ltc2263-12/ltc2264-12/ ltc2265-12 12-bit, 25msps/40msps/65msps 1.8v dual adcs, ultralow power 99mw/126mw/191mw, 70.5db snr, 85db sfdr, serial lvds outputs, 6mm 6mm qfn-36 ltc2266-14/ltc2267-14/ ltc2268-14 14-bit, 80msps/105msps/125msps 1.8v dual adcs, ultralow power 216mw/250mw/293mw, 73.4db snr, 85db sfdr, serial lvds outputs, 6mm 6mm qfn-36 ltc2266-12/ltc2267-12/ ltc2268-12 12-bit, 80msps/105msps/125msps 1.8v dual adcs, ultralow power 216mw/250mw/293mw, 70.5db snr, 85db sfdr, serial lvds outputs, 6mm 6mm qfn-36 rf mixers/demodulators ltc5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator ltc5527 400mhz to 3.7ghz high linearity downconverting mixer 24.5dbm iip3 at 900mhz, 23.5dbm iip3 at 3.5ghz, nf = 12.5db, 50 single-ended rf and lo ports ltc5557 400mhz to 3.8ghz high linearity downconverting mixer 23.7dbm iip3 at 2.6ghz, 23.5dbm iip3 at 3.5ghz, nf = 13.2db, 3.3v supply operation, integrated transformer ltc5575 800mhz to 2.7ghz direct conversion quadrature demodulator high iip3: 28dbm at 900mhz, integrated lo quadrature generator, integrated rf and lo transformer amplifiers/filters ltc6412 800mhz, 31db range, analog-controlled variable gain amplifier continuously adjustable gain control, 35dbm oip3 at 240mhz, 10db noise figure, 4mm 4mm qfn-24 ltc6420-20 1.8ghz dual low noise, low distortion differential adc drivers for 300mhz if fixed gain 10v/v, 1nv/ hz total input noise, 80ma supply current per amplifier, 3mm 4mm qfn-20 ltc6421-20 1.3ghz dual low noise, low distortion differential adc drivers fixed gain 10v/v, 1nv/ hz total input noise, 40ma supply current per amplifier, 3mm 4mm qfn-20 ltc6605-7/ ltc6605-10/ ltc6605-14 dual matched 7mhz/10mhz/14mhz filters with adc drivers dual matched 2nd order lowpass filters with differential drivers, pin-programmable gain, 6mm 3mm dfn-22 receiver subsystems ltm9002 14-bit dual channel if/baseband receiver subsystem integrated high speed adc, passive filters and fixed gain differential ampli? ers

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